In semiconductor manufacturing, the International Roadmap for Devices and Systems defines the 5 nm process as the MOSFET technology node following the 7 nm node. In 2020, Samsung and TSMC entered volume production of 5 nm chips, manufactured for companies including Apple, Marvell, Huawei and Qualcomm.[1][2]
The term "5 nanometer" has no relation to any actual physical feature (such as gate length, metal pitch or gate pitch) of the transistors. It is a commercial or marketing term used by the chip fabrication industry to refer to a new, improved generation of silicon semiconductor chips in terms of increased transistor density (i.e. a higher degree of miniaturization), increased speed and reduced power consumption.[3][4]
Quantum tunnelling effects through the gate oxide layer on 7 nm and 5 nm transistors became increasingly difficult to manage using existing semiconductor processes.[5] Single-transistor devices below 7 nm were first demonstrated by researchers in the early 2000s. In 2002, an IBM research team including Bruce Doris, Omer Dokumaci, Meikei Ieong and Anda Mocuta fabricated a 6-nanometre silicon-on-insulator (SOI) MOSFET.[6][7]
In 2003, a Japanese research team at NEC, led by Hitoshi Wakabayashi and Shigeharu Yamagami, fabricated the first 5 nm MOSFET.[8][9]
In 2015, IMEC and Cadence had fabricated 5 nm test chips. The fabricated test chips are not fully functional devices but rather are to evaluate patterning of interconnect layers.[10][11]
In 2015, Intel described a lateral nanowire (or gate-all-around) FET concept for the 5 nm node.[12]
In 2017, IBM revealed that they had created 5 nm silicon chips,[13] using silicon nanosheets in a gate-all-around configuration (GAAFET), a break from the usual FinFET design. The GAAFET transistors used had 3 nanosheets stacked on top of each other, covered in their entirety by the same gate, just like FinFETs usually have several physical fins side by side that are electrically a single unit and are covered in their entirety by the same gate. IBM's chip measured 50 mm2 and had 600 million transistors per mm2, for a total of 50 billion transistors.[14][15]
In April 2019, Samsung Electronics announced they had been offering their 5 nm process (5LPE) tools to their customers since 2018 Q4.[16] In April 2019, TSMC announced that their 5 nm process (CLN5FF, N5) had begun risk production, and that full chip design specifications were now available to potential customers. The N5 process can use EUVL on up to 14 layers, compared to only 5 or 4 layers in N6 and N7++.[17] For the expected 28 nm minimum metal pitch, SALELE is the proposed best patterning method.[18]
For their 5 nm process, Samsung started process defect mitigation by automated check and fix, due to occurrence of stochastic (random) defects in the metal and via layers.[19]
In October 2019, TSMC started sampling 5 nm A14 processors for Apple.[20]
In December 2019, TSMC announced an average yield of approximately 80%, with a peak yield per wafer of over 90% for their 5 nm test chips with a die size of 17.92 mm2.[21] In mid 2020 TSMC claimed its (N5) 5 nm process offered 1.8x the density of its 7 nm N7 process, with 15% speed improvement or 30% lower power consumption; an improved sub-version (N5P) was claimed to improve on N5 with +5% speed or -10% power.[22]
On October 13, 2020, Apple announced a new iPhone 12 lineup using the A14, together with the Huawei Mate 40 lineup using the HiSilicon Kirin 9000, which were the first devices to be commercialized on TSMC's 5 nm node. Later, on November 10, 2020, Apple also revealed three new Mac models using the Apple M1, another 5 nm chip. According to Semianalysis, the A14 processor has a transistor density of 134 million transistors per mm2.[23]
| Samsung[24] | TSMC[25] | IRDS roadmap 2017[26] | Intel[27] | ||
|---|---|---|---|---|---|
| Process name (nm for TSMC & Samsung) | 5LPE | N5 | 7 nm | 5 nm | 4 |
| Transistor density (MTr/mm2) | 127 | 173[28] | ? | ? | ~200 |
| SRAM bit-cell size (μm2) | 0.026 | 0.017–0.019 | 0.027[29] | 0.020[29] | Unknown |
| Transistor gate pitch (nm) | 57 | 48 | 48 | 42 | Unknown |
| Interconnect pitch (nm) | 36 | 28[30] | 28 | 24 | Unknown |
| Risk production year | 2018[16] | 2019[17] | 2019 | 2021 | 2022 |
Transistor gate pitch is also referred to as CPP (contacted poly pitch) and interconnect pitch is also referred to as MMP (minimum metal pitch).[31][32]
3 nm (3-nanometer) is the usual term for the next node after 5 nm. As of 2021, TSMC plans to commercialize the 3 nm node for 2022, while Samsung and Intel have plans for 2023.[33][34][35][36]
3.5 nm has also been given as a name for the first node beyond 5 nm.[37]
Intel presented a paper that generated sparks and fueled speculation regarding the future direction of the leading-edge IC industry. The company described a next-generation transistor called the nanowire FET, which is a finFET turned on its side with a gate wrapped around it. Intel's nanowire FET, sometimes called a gate-all-around FET, is said to meet the device requirements for 5nm, as defined by the International Technology Roadmap for Semiconductors (ITRS).